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Low phase noise VCXO output for the 24MHz to
50MHz range (-130 dBc at 10kHz offset).
CMOS output.
12 to 25MHz crystal input.
Integrated variable capacitors.
Selectable High Drive (30mA) or Standard Drive
(10mA) output.
Wide pull range (+/- 250 ppm typ.).
Low jitter (RMS): 3ps period (1 sigma).
3.3V operation.
Available in 8-Pin SOIC.
PIN CONFIGURATION
XOUT
N/C
VCON
GND
1
2
3
4
8
7
6
5
XIN
N/C
VDD
CLK
PLL502-02
DESCRIPTION
The PLL502-02 is a low cost, high performance, low
phase noise VCXO, providing less than -130dBc at
10kHz offset in the 24MHz to 50MHz operating
range. The very low jitter (3 ps RMS period jitter)
makes this chip ideal for applications requiring volt-
age controlled frequency sources. Input crystal can
range from 12 to 25MHz (fundamental resonant
mode).
OUTPUT RANGE
MULTIPLIER
x2
FREQUENCY
RANGE
24 - 50MHz
OUTPUT
BUFFER
CMOS
BLOCK DIAGRAM
VCO
Divider
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
XIN
XOUT
XTAL
OSC
VARICAP
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 1
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