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PLHS501IA Datasheet

  • PLHS501IA

  • Programmable macro logic PML

  • 85.55KB

  • 12頁

  • PHILIPS

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Philips Semiconductors Programmable Logic Devices
Product specification
Programmable macro logic
PML鈩?/div>
PLHS501/PLHS501I
FEATURES
鈥?/div>
Programmable Macro Logic device
鈥?/div>
Full connectivity
鈥?/div>
TTL compatible
鈥?/div>
SNAP development system:
鈥?/div>
Supports third-party schematic entry
formats
鈥?/div>
Macro library
鈥?/div>
Versatile netlist format for design
portability
鈥?/div>
Logic, timing, and fault simulation
PIN CONFIGURATION
A Package
(52-pin PLCC)
I
17
I
16
I
15
I
14
I
13
I
12
I
11
I
10
I
9
7
V
CC
8
I
18
9
I
19
10
I
20
11
I
21
12
I
22
13
I
23
14
B
4
15
B
5
16
B
6
17
B
7
18
O
0
19
GND 20
21 22 23 24 25 26 27 28 29 30 31 32 33
6
5
4
3
2
1
I
8
I
7
I
6
I
5
46 V
CC
45 I
4
44 I
3
43 I
2
42 I
1
41 I
0
40 B
3
39 B
2
38 B
1
37 B
0
36 X
7
35 X
6
34 GND
52 51 50 49 48 47
鈥?/div>
Delay per internal NAND function = 6.5ns
(typ)
鈥?/div>
Testable in unprogrammed state
鈥?/div>
Security fuse allows protection of
proprietary designs
STRUCTURE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
X
0
X
1
X
2
X
3
X
4
X
5
鈥?/div>
NAND gate based architecture
鈥?/div>
72 foldback NAND terms
鈥?/div>
136 input-wide logic terms
鈥?/div>
44 additional logic terms
鈥?/div>
24 dedicated inputs (I
0
鈥?I
23
)
鈥?/div>
8 bidirectional I/Os with individual 3-State
enable:
鈥?/div>
4 Active-High (B
4
鈥?B
7
)
鈥?/div>
4 Active-Low (B
0
鈥?B
3
)
DESCRIPTION
The PLHS501 is a high-density Bipolar
Programmable Macro Logic device. PML
incorporates a programmable NAND
structure. The NAND architecture is an
efficient method for implementing any logic
function. The SNAP software development
system provides a user friendly environment
for design entry. SNAP eliminates the need
for a detailed understanding of the PLHS501
architecture and makes it transparent to the
user. PLHS501 is also supported on the
Philips Semiconductors SNAP software
development systems.
The PLHS501 is ideal for a wide range of
microprocessor support functions, including
bus interface and control applications.
The PLHS501 is also processed to industrial
requirements for operation over an extended
temperature range of 鈥?0擄C to +85擄C and
supply voltage of 4.5V to 5.5V.
ARCHITECTURE
The core of the PLHS501 is a programmable
fuse array of 72 NAND gates. The output of
each gate folds back upon itself and all other
NAND gates. In this manner, full connectivity
of all logic functions is achieved in the
PLHS501. Any logic function can be created
within the core of the device without wasting
valuable I/O pins. Furthermore, a speed
advantage is acquired by implementing
multi-level logic within a fast internal core
without incurring any delays from the I/O
buffers.
鈥?/div>
16 dedicated outputs:
鈥?/div>
4 Active-High outputs
O
0
, O
1
with common 3-State enable
O
2
, O
3
with common 3-State enable
鈥?/div>
4 Active-Low outputs:
O
4
, O
5
with common 3-State enable
O
6
, O
7
with common 3-State enable
鈥?/div>
8 Exclusive-OR outputs:
X
0
, X
1
with common 3-State enable
X
2
, X
3
with common 3-State enable
X
4
, X
5
with common 3-State enable
X
6
, X
7
with common 3-State enable
PML is a trademark of Philips Semiconductors
October 22, 1993
1
853鈥?207 11164

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