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PLC42VA12N Datasheet

  • PLC42VA12N

  • CMOS programmable multi-function PLD 42 】 105 】 12

  • 20頁

  • PHILIPS

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Philips Semiconductors Programmable Logic Devices
Product specification
CMOS programmable multi-function PLD
(42
脳
105
脳
12)
PLC42VA12
DESCRIPTION
The new PLC42VA12 CMOS PLD from
Philips Semiconductors exhibits a unique
combination of the two architectural concepts
that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output
Macro Cell (OMC) embodies all the
advantages and none of the disadvantages
associated with the 鈥淰鈥?type Output Macro
Cell devices. This new design, combined with
added functionality of two programmable
arrays, represents a significant advancement
in the configurability and efficiency of
multi-function PLDs.
The most significant improvement in the
Output Macro Cell structure is the
implementation of the register bypass
function. Any of the 10 J-K/D registers can be
individually bypassed, thus creating a
combinatorial I/O path from the AND array to
the output pin. Unlike other 鈥淰鈥?type devices,
the register in the PLC42VA12 Macro Cell
remains fully functional as a buried register.
Both the combinatorial I/O and buried register
have separate input paths (from the AND
array). In most V-type architectures, the
register is lost as a resource when the cell is
configured as a combinatorial I/O. This
feature provides the capability to operate the
buried register independently from the
combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS
device. Designs can be generated using
Philips Semiconductors SNAP PLD design
software packages or one of several other
commercially available JEDEC standard PLD
design software packages.
FEATURES
鈥?/div>
High-speed EPROM-based CMOS
Multi-Function PLD
鈥?/div>
Super set of 22V10, 32VX10 and
20RA10 PAL廬 ICs
PIN CONFIGURATIONS
FA and N Pack-
ages
I0/CLK
I1
I2
I3
I4
I5
I6
I7
I8
1
2
3
4
5
6
7
8
9
24 V
CC
23 M9
22 M8
21 M7
20 M6
19 M5
18 M4
17 M3
16 M2
15 M1
14 M0
13 I9/OE
鈥?/div>
Two fully programmable arrays eliminate
鈥淧-term Depletion鈥?/div>
鈥?/div>
Up to 64 P-terms per OR function
鈥?/div>
Improved Output Macro Cell Structure
鈥?/div>
Individually programmable as:
* Registered Output with feedback
* Registered Input
* Combinatorial I/O with Buried Register
* Dedicated I/O with feedback
* Dedicated Input (combinatorial)
鈥?/div>
Bypassed Registers are 100% functional
with separate input and feedback paths
鈥?/div>
Individual Output Enable control
functions
* From pin or AND array
B0 10
B1 11
GND 12
鈥?/div>
Reprogrammable 鈥?100% tested for
programmability
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
鈥?/div>
Eleven clock sources
鈥?/div>
Register Preload and Diagnostic Test Mode
Features
A Package
I2
4
I0/
I1 CLK N/C V
CC
M9 M8
3
2
1
28
27
26
25 M7
24 M6
23 M5
22 N/C
21 M4
20 M3
19 M2
12
13
14
15
16
17
18
鈥?/div>
Security fuse
APPLICATIONS
鈥?/div>
Synchronous
鈥?/div>
Asynchronous
I3
I4
I5
N/C
I6
5
6
7
8
9
鈥?/div>
Mealy or Moore State Machines
鈥?/div>
Multiple, independent State Machines
鈥?/div>
10-bit ripple cascade
鈥?/div>
Sequence recognition
鈥?/div>
Bus Protocol generation
鈥?/div>
Industrial control
鈥?/div>
A/D Scanning
I7 10
I8 11
B0 B1 GND N/C I9/ M0 M1
OE
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION
24-Pin Ceramic Dual In-Line with window,
Reprogrammable (300mil-wide)
24-Pin Plastic Dual In-Line,
One Time Programmable (300mil-wide)
28-Pin Plastic Leaded Chip Carrier,
One Time Programmable (450mil-wide)
ORDER CODE
PLC42VA12FA
PLC42VA12N
PLC42VA12A
DRAWING NUMBER
1478A
0410D
0401F
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993
73
853鈥?414 11164

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