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PKD01EY Datasheet

  • PKD01EY

  • Monolithic Peak Detector with Reset-and-Hold Mode

  • 18頁

  • AD

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a
FEATURES
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/ s
Low Droop Rate
T
A
= 25 C: 0.1 mV/ms
T
A
= 125 C: 10 mV/ms
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
Monolithic Peak Detector
with Reset-and-Hold Mode
PKD01
FUNCTIONAL BLOCK DIAGRAM
+IN
鈥揑N
OUTPUT
V+
V鈥?/div>
鈥?/div>
CMP
+
LOGIC
GND
V鈥?/div>
OUTPUT
BUFFER
GATED
"g
m
"
AMP
A
鈥?/div>
D
1
+
C
OUTPUT
DET
鈥揑N
+IN
鈥?/div>
+
鈥揑N
+IN
鈥?/div>
B
+
GATED
"g
m
"
AMP
PKD01
GENERAL DESCRIPTION
The PKD01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
PKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
sacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
when charge injection and droop rate error reduction are
primary goals.
Innovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (g
m
) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
g
m
amplifiers simplify internal frequency compensation, minimize
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
steered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
ently low zero-scale error is further reduced by active Zener-Zap
trimming to optimize overall accuracy.
RST
RST
0
0
1
1
DET
0
1
1
0
OPERATIONAL MODE
PEAK DETECT
PEAK HOLD
RESET
INDETERMINATE
C
H
SWITCHES SHOWN FOR:
RST = 鈥?,鈥?/div>
DET
= 鈥?鈥?/div>
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Through the
DET
control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
漏 Analog Devices, Inc., 2001

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