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PI74FCT16322601
18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
聲 PI74FCT16322601 is designed for low voltage operation
聲 V
CC
= 2.3V to 3.6V
聲 Hysteresis on all inputs
聲 Typical V
OLP
(Output Ground Bounce) < 0.8V
at V
CC
= 3.3V, T
A
= 25擄C
聲 Typical V
OHV
(Output V
OH
Undershoot) < 2.0V
at V
CC
= 3.3V, T
A
= 25擄C
聲 Inputs/Outputs have equivalent 26 ohm series resistors,
no external resistors are required.
聲 Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
聲 Industrial operation at 聳40擄C to +85擄C
聲 Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A56)
聳 56-pin 300 mil wide plastic SSOP (V56)
Product Description
Pericom Semiconductor聮s PI74FCT3 series of logic circuits
are produced in the Company聮s advanced 0.5 micron
CMOS technology, achieving industry leading speed.
The PI74FCT16322601 uses D-type latches and D-type
flip-flops with 3-state outputs to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by Output Enable
(OEAB and OEBA), Latched Enable (LEAB and LEBA),
and Clock (CLKAB and CLKBA) inputs. The clock can be
controlled by the Clock Enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a high or
low logic level. If LEAB is low, the A-bus is stored in the
latch/flip-flop on the high-to-low transition of CLKAB.
When OEAB is low, the outputs are active. When OEAB
is HIGH, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the inputs/outputs
include 26鈩?series resistors.
To ensure the high-impedance state during power up or
power down, OE should be tied to Vcc through a pull-up
resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver.
The PI74FCT16322601 has 聯(lián)Bus Hold聰 which retains the
data input聮s last state whenever the data input goes to
high-impedance preventing 聯(lián)floating聰 inputs and
eliminating the need for pullup/down resistors.
Logic Block Diagram
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
3
CE
1D
C1
CLK
CE
1D
C1
CLK
54
B1
To 17 Other Channels
1
PS8143 10/22/97
1
2
3
4
5
6
