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PI74FCT16244/162244/162H244T
PI74FCT16244T
16-BIT BUFFER/LINE DRIVERS
PI74FCT162244T
PI74FCT162H244T
Product Features:
Common Features:
鈥?PI74FCT16244T, PI74FCT162244T and
PI74FCT162H244T are high-speed, low power devices
with high current drive.
鈥?Vcc = 5V
鹵10%
鈥?Hysteresis on all inputs
鈥?Packages available:
鈥?48-pin 240 mil wide plastic TSSOP (A48)
鈥?48-pin 300 mil wide plastic SSOP (V48)
鈥?Device models available upon request.
PI74FCT16244T Features:
鈥?High output drive: I
OH
= 鈥?2 mA; I
OL
= 64 mA
鈥?Power off disable outputs permit "live insertion"
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162244T Features:
鈥?Balanced output drivers:
鹵24
mA
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H244T Features:
鈥?Bus Hold retains last active bus state during 3-state
鈥?Eliminates the need for external pull-up resistors
Fast CMOS 16-Bit
Buffer/Line Drivers
Product Description:
Pericom Semiconductor鈥檚 PI74FCT series of logic circuits are pro-
duced in the Company鈥檚 advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16244T, PI74FCT162244T, and PI74FCT162H244T
are non-inverting 16-bit buffer/line drivers designed for applications
driving high capacitance loads and low impedance backplanes.
These high-speed, low power devices offer bus/backplane interface
capability and a flow-through organization for ease of board layout.
These devices are designed with three-state controls to operate in a
Quad-Nibble, Dual-Byte, or a single 16-bit word mode.
The PI74FCT16244T output buffers are designed with a Power-Off
disable allowing "live insertion" of boards when used as backplane
drivers.
The PI74FCT162244T has
鹵24
mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H244T has "Bus Hold" which retains the input's
last state whenever the input goes to high-impedance preventing
"floating" inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1
OE
3
OE
1
A
0
1
Y
0
3
A
0
3
Y
0
1
A
1
1
Y
1
3
A
1
3
Y
1
1
A
2
1
Y
2
3
A
2
3
Y
2
1
A
3
1
Y
3
3
A
3
3
Y
3
2
OE
4
OE
2
A
0
2
Y
0
4
A
0
4
Y
0
2
A
1
2
Y
1
4
A
1
4
Y
1
2
A
2
2
Y
2
4
A
2
4
Y
2
2
A
3
2
Y
3
4
A
3
4
Y
3
161
PS2031A 03/11/96
PERICOM
1
2
3
4
5
6
