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PI74FCT16827T/162827/162H827T
PI74FCT16827T
20-BIT BUFFERS
PI74FCT162827T
PI74FCT162H827T
Fast CMOS
20-Bit Buffers
Common Features:
聲 PI74FCT16827T, PI74FCT162827T, and PI74FCT2H827T
are high-speed,
low power devices with high current drive
聲 V
CC
= 5V 鹵10%
聲 Hysteresis on all inputs
聲 Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
PI74FCT16827T Features:
聲 High output drive: I
OH
= 聳32 mA; I
OL
= 64 mA
聲 Power off disable outputs permit "live insertion"
聲 Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162827T Features:
聲 Balanced output drivers: 鹵24 mA
聲 Reduced system switching noise
聲 Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H827T Features:
聲 Bus Hold retains last active bus state during 3-state
聲 Eliminates the need for external pull-up resistors
Product Features
Product Description
Pericom Semiconductor聮s PI74FCT series of logic circuits are pro-
duced in the Company聮s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16827T, PI74FCT162827T, and PI74FCT162H827T are
20-bit wide bus drivers designed to provide buffering and high-
performance bus interfacing for wide data/address paths or buses
with parity. Two pair of nanded output enable controls allow the
devices to be operated as two 10-bit buffers or as one 20-bit buffer.
Signal pins are arranged in a flow-through organization for ease of
layout and hysteresis is designed into all inputs to improve noise
margin.
The PI74FCT16827T output buffers are designed with a Power-Off
disable function allowing 聯(lián)live insertion聰 of boards when the
devices are used as backplane drives.
The PI74FCT162827T has 鹵24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H827T has 聯(lián)Bus Hold聰 which retains the input's last
state whenever the input goes to high-impedance preventing
聯(lián)floating聰 inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1
OE
1
1
OE
2
2
OE
1
2
OE
2
1
Y
1
1
A
1
2
A
1
2
Y
1
To 9 other channels
To 9 other channels
1
PS2041A 03/11/96
1
2
3
4
5
6
7
