Common Features:
聲 PI74FCT16823T and PI74FCT162823T are high-speed, low
power devices with high current drive.
聲 V
CC
= 5V 鹵10%
聲 Hysteresis on all inputs
聲 Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide palstic SSOP (V)
PI74FCT16823T Features:
聲 High output drive: I
OH
= 聳32 mA; I
OL
= 64 mA
聲 Power off disable outputs permit 聯(lián)live insertion聰
聲 Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162823T Features:
聲 Balanced output drivers: 鹵24 mA
聲 Reduced system switching noise
聲 Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H823T Features:
聲 Bus Hold retains last active bus state during 3-state
聲 Eliminates the need for external pull-up resistors
Product Features:
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74FCT16823T/162823/162H823T
PI74FCT16823T
18-BIT REGISTERS
PI74FCT162823T
PI74FCT162H823T
Fast CMOS
18-Bit Registers
Product Description
Pericom Semiconductor聮s PI74FCT series of logic circuits are pro-
duced in the Company聮s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16823T, PI74FCT162823T and PI74FCT162H823 are 18-
bit wide registers with clock enable (xCLKEN) and clear (xCLR)
controls that make these devices especially suitable for parity bus
interfacing in high-performance systems. The devices can be operated
as two 9-bit registers or one 18-bit register using the control inputs.
Signal pins are arranged in a flow-through organization for ease of
layout and hysteresis is designed into all inputs to improve noise
margin.
The PI74FCT16823T output buffers are designed with a Power-Off
disable function allowing 聯(lián)live insertion聰 of boards when the
devices are used as backplane drives.
The PI74FCT162823T has 鹵24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H823T has 聯(lián)Bus Hold聰 which retains the input聮s
last state whenever the input goes to high-impedance preventing
聯(lián)floating聰 inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1
OE
1
CLR
1
CLK
1
CLKEN
2
OE
2
CLR
2
CLK
2
CLKEN
R
C
D
1
D
1
1
Q
1
R
C
D
2
D
1
2
Q
1
To 8 other channels
To 8 other channels
1
PS2040A 03/11/96
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2
3
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