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PI74FCT16652ATV Datasheet

  • PI74FCT16652ATV

  • Dual 8-bit Bus Transceiver

  • 6頁(yè)

  • ETC

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PI74FCT16652/162652T
16-BIT REGISTERED TRANSCEIVERS
PI74FCT16652T
PI74FCT162652T
Product Features
Fast CMOS 16-Bit
Registered Transceivers
Common Features:
聲 PI74FCT16652T and PI74FCT162652T are high-speed, low
power devices with high current drive.
聲 Vcc = 5V 鹵10%
聲 Hysteresis on all inputs
聲 Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
PI74FCT16652T Features:
聲 High output drive: I
OH
= 聳32 mA; I
OL
= 64 mA
聲 Power off disable outputs permit 聯(lián)live insertion聰
聲 Typical V
OLP
(Output Ground Bounce)
< 1.0V at V
CC
= 5V, T
A
= 25擄C
PI74FCT162652T Features:
聲 Balanced output drivers: 鹵24 mA
聲 Reduced system switching noise
聲 Typical V
OLP
(Output Ground Bounce)
< 0.6V at V
CC
= 5V, T
A
= 25擄C
Product Description
Pericom Semiconductor's PI74FCT series of logic circuits are pro-
duced in the Company聮s advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16652T and PI74FCT162652T are 16-bit registered
transceivers organized as two independent 8-bit bus transceivers
designed with 3-State D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the data bus or from
the internal storage registers. Each 8-bit transceiver utilizes the
enable controls (xOEAB and x OEBA) to control the transceiver
functions. The Select (xSAB and xSBA) control pins are used to
select either real-time or stored data transfer. The circuitry used for
select control will eliminate the typical decoding glitch that occurs
in a multiplexer during the transition between real-time and stored
data. A low input level selects real-time data and a high selects stored
data.
The PI74FCT16652T output buffers are designed with a Power-Off
disable allowing 聯(lián)live insertion聰 of boards when used as backplane
drivers.
The PI74FCT162652T has 鹵24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
Logic Block Diagram
1
OEAB
2
OEAB
1
OEBA
2
OEBA
1
CLKBA
1
SBA
2
CLKBA
2
SBA
1
CLKAB
1
SAB
2
CLKAB
2
SAB
B REG
D
C
B REG
D
C
1
A
0
2
A
0
A REG
D
C
1
B
0
A REG
D
C
2
B
0
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
1
PS2079A 01/15/95

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