音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PI74FCT162H543CTV Datasheet

  • PI74FCT162H543CTV

  • Dual 8-bit Bus Transceiver

  • 7頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

PI74FCT16543T
PI74FCT162543T
PI74FCT162H543T
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Fast CMOS 16-Bit
Latched Transceivers
Product Features:
Common Features:
鈥?PI74FCT16543T, PI74FCT162543T and PI74FCT162H543T
are high-speed,
low power devices with high current drive.
鈥?V
CC
= 5V 鹵10%
鈥?Hysteresis on all inputs
鈥?Packages available:
鈥?56-pin 240 mil wide plastic TSSOP (A)
鈥?56-pin 300 mil wide plastic SSOP (V)
PI74FCT16543T Features:
鈥?High output drive: I
OH
= 鈥?2 mA; I
OL
= 64 mA
鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162543T Features:
鈥?Balanced output drivers: 鹵24 mA
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H543T Features:
鈥?/div>
Bus Hold retains last active state during 3-state
鈥?Eliminates the need for external pull-up resistors
Product Description:
Pericom Semiconductor鈥檚 PI74FCT series of logic circuits are pro-
duced in the Company鈥檚 advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
ThePI74FCT16543T,PI74FCT162543TandPI74FCT162H543T are 16-
bit latched transceivers organized with two sets of eight
D-type latches with separate input and output controls for each set.
For data flow from A to B, for example, the A-to-B Enable
(xCEAB) input must be LOW in order to enter data from xAx or to
take data from xBx, as indicated in the Truth Table. With xCEAB
LOW, a LOW signal makes the A-to-B latches transparent; a
subsequent LOW-to-HIGH transition of the xLEAB signal puts the
A latches in the storage mode and their outputs no longer change the
A inputs. With xCEAB and xOEAB both LOW, the 3-state B output
buffers are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the xCEBA,
xLEBA, and xOEBA inputs.
The PI74FCT16543T output buffers are designed with a Power-Off
disable allowing 鈥渓ive insertion鈥漮f boards when used as backplane
drivers.
The PI74FCT162543T has 鹵24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H543T has 鈥淏us Hold鈥?which retains the input鈥檚
last state whenever the input goes to high-impedance preventing
鈥渇loating鈥?inputs and eliminating the need for pull-up/down
resistors.
2
OEBA
Logic Block Diagram
1
OEBA
1
CEBA
2
CEBA
1
LEBA
1
OEAB
2
LEBA
2
OEAB
1
CEAB
2
CEAB
1
LEAB
1
A
0
C
1
B
0
2
LEAB
2
A
0
C
2
B
0
D
C
C
D
D
D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
1
PS2038B
01/10/01

PI74FCT162H543CTV相關(guān)型號(hào)PDF文件下載

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù):
賣家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào),
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見,您的參與是維庫提升服務(wù)的動(dòng)力!意見一經(jīng)采納,將有感恩紅包奉上哦!