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power devices with high current drive.
鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162511T Features:
鈥?High output drive: I
OL
/I
OH
= 24 mA
鈥?Open drain parity error allows wire-OR
鈥?Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
鈥?Balanced output drivers: 鹵24 mA
鈥?Series current limiting resistors
Fast CMOS 16-Bit Registered/Latched
Transceiver With Parity
Product Description:
Pericom Semiconductor鈥檚 PI74FCT series of logic circuits are pro-
duced in the Company鈥檚 advanced 0.8 micron CMOS technology,
achieving industry leading speed grades.
The PI74FCT16511T and PI74FCT162511T are high-speed, low-
power 16-bit registered/latched transceiver with parity which
combines D-type latches and D-type flip-flops to allow data flow
in transparent, latched or clocked modes. It has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A
direction. Error checking is done at the byte level with separate
parity bits for each byte. One error flag for each direction (A-to-B
or B-to-A) exists to indicate an error for either byte in either
direction. The parity error flags which are open drain outputs, can
be tied together and/or tied with flags from other devices to form a
single error flag or interrupt. To disable the error flag during
combinational transitions, a designer can disable the parity error
flag by the OExx control pins.
The operation in A-to-B direction is controlled by LEAB, CLKAB
and OEAB control pins, and the operation in B-to-A direction is
controlled by LEBA, CLKBA and OEBA control pins. GEN/CHK
is used to select the operation of A-to-B direction, while B-to-A
direction is always in checking mode. The ODD/EVEN select is
common between the two directions. Independent operation can be
achieved between the two directions by using the corresponding
control lines except for the ODD/EVEN control.
Simplified Logic Block Diagram
LEAB
CLKAB
Data
Parity, data
16
Parity
GEN/CHK
Byte
Parity
Generator/
Checker
2
Latch/
Register
18
B0-15
PB1,2
PERB
(Open Drain)
OEAB
A0-15
PA1,2
ODD/EVEN
LEBA
CLKBA
Parity, data
18
OEBA
PERA
(Open Drain)
Latch/
Register
Byte
Parity
Checking
Parity, data
18
1
PS2080A 01/15/95
PERICOM
1
2
3
4
5
6
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