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PI74FCT16373/162373/162H373T
PI74FCT16373T
16-BIT TRANSPARENT LATCHES
PI74FCT162373T
PI74FCT162H373T
Fast CMOS 16-Bit
Transparent Latches
Product Features
Common Features:
聲 PI74FCT16373T, PI74FCT162373T, and
PI74FCT162H373T are high-speed,
low power devices with high current drive.
聲 Vcc = 5V 鹵10%
聲 Hysteresis on all inputs
聲 Packages available:
聳 48-pin 240 mil wide plastic TSSOP (A)
聳 48-pin 300 mil wide plastic SSOP (V)
PI74FCT16373T Features:
聲 High output drive: I
OH
= 聳32 mA; I
OL
= 64 mA
聲 Power off disable outputs permit "live insertion"
聲 Typical V
OLP
(Output Ground Bounce) < 1.0V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162373T Features:
聲 Balanced output drivers: 鹵24 mA
聲 Reduced system switching noise
聲 Typical V
OLP
(Output Ground Bounce) < 0.6V
at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H373T Features:
聲 Bus Hold retains last active bus state during 3-state
聲 Eliminates the need for external pull-up resistors
Product Description
Pericom Semiconductor聮s PI74FCT series of logic circuits are pro-
duced using the Company聮s advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
The PI74FCT16373T, PI74FCT162373T, and PI74FCT162H373T
are 16-bit transparent latches designed with 3-state outputs and are
intended for bus oriented applications. The Output Enable and
Latch Enable controls are organized to operate as two 8-bit latches
or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops
appear transparent to the data. The data that meets the set-up time
when LE is LOW is latched. When OE is HIGH, the bus output is
in the high impedance state.
The PI74FCT16373T output buffers are designed with a Power-Off
disable allowing 聯(lián)live insertion聰 of boards when used as backplane
drivers.
The PI74FCT162373T has 鹵24 mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H373T has 聯(lián)Bus Hold聰 which retains the input聮s
last state whenever the input goes to high-impedance preventing
聯(lián)floating聰 inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1
OE
2
OE
1
LE
2
LE
1
D
0
D
1
O
0
2
D
0
D
2
O
0
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
1
PS2033A 03/11/96
1
2
3
4
5
6
7
