21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
鈥?Power off disable outputs permit 鈥渓ive insertion鈥?/div>
鈥?Typical V
OLP
(Output Ground Bounce)
< 1.0V at V
CC
= 5V, T
A
= 25擄C
PI74FCT162245T Features
鈥?Balanced output drivers:
鹵24mA
鈥?Reduced system switching noise
鈥?Typical V
OLP
(Output Ground Bounce)
< 0.6V at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H245T Features
鈥?Bus Hold retains last active bus state during Three-State
鈥?Eliminates the need for external pull-up resistors
Product Description
Pericom Semiconductor鈥檚 PI74FCT series of logic circuits are
produced using the Company鈥檚 advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
The PI74FCT16245T, PI74FCT162245T, and PI74FCT162H245T
are 16-bit bidirectional transceivers designed for asynchronous
two-way communication between data buses. The direction control
input pin (xDIR) determines the direction of data flow through the
bidirectional transceiver. The Direction and Ouput Enable controls
are designed to operate these devices as either two independent
8-bit transceivers or one 16-bit transceiver. The output enable (OE)
input, when HIGH, disables both A and B ports by placing them in
HIGH Z condition.
The PI74FCT16245T output buffers are designed with a Power-
Off disable allowing 鈥渓ive insertion鈥?of boards when used as
backplane drivers.
The PI74FCT162245T has
鹵24mA
balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H245T has 鈥淏us Hold鈥?which retains the input鈥檚
last state whenever the input goes to high-impedance preventing
鈥渇loating鈥?inputs and eliminating the need for pull-up/down resistors.
Logic Block Diagram
1
DIR
1
OE
1
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
3
1
B
3
1
A
4
1
B
4
1
A
5
1
B
5
1
A
6
1
B
6
1
A
7
1
B
7
2
A
7
2
B
7
2
A
6
2
B
6
2
A
5
2
B
5
2
A
4
2
B
4
2
A
3
2
B
3
2
A
2
2
B
2
2
A
1
2
B
1
2
A
0
2
B
0
2
DIR
2
OE
1
PS2032D
05/17/99
PERICOM
1
2
3
4
5
6
