PI74FCT16244T
PI74FCT162244T
PI74FCT162H244T
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Fast CMOS 16-Bit Buffer/Line Drivers
Product Features
Common Features
聲
PI74FCT16244T, PI74FCT162244T and PI74FCT162H244T
are high-speed, low-power devices with high-current drive
V
CC
= 5V 鹵10%
聲
Hysteresis on all inputs
聲
Packages available:
聳 48-pin 240 mil wide plastic TSSOP (A)
聳 48-pin 300 mil wide plastic SSOP (V)
聳 48-pin 173 mil wide plastic TVSOP (K)
聲
Device models available upon request
PI74FCT16244T Features
聲
High output drive: I
OH
= 聳32mA; I
OL
= 64mA
聲
Power off disable outputs permit "live insertion"
聲
Typical V
OLP
(Output Ground Bounce)
< 1.0V at V
CC
= 5V, T
A
= 25擄C
PI74FCT162244T Features
聲
Balanced output drivers: 鹵24mA
聲
Reduced system switching noise
聲
Typical V
OLP
(Output Ground Bounce)
< 0.6V at V
CC
= 5V, T
A
= 25擄C
PI74FCT162H244T Features
聲
Bus Hold retains last active bus state during 3-State
聲
Eliminates the need for external pull-up resistors
Product Description
Pericom Semiconductor聮s PI74FCT series of logic circuits are
produced using the Company聮s advanced 0.6 micron CMOS
technology, achieving industry leading speed grades.
PI74FCT16244T, PI74FCT162244T, and PI74FCT162H244T are
non-inverting 16-bit buffer/line drivers designed for applications
driving high capacitance loads and low impedance backplanes.
These high-speed, low power devices offer bus/backplane interface
capability and a flow-through organization for ease of board
layout. These devices are designed with three-state controls to
operate in a Quad-Nibble, Dual-Byte, or a single 16-bit word
mode.
The PI74FCT16244T output buffers are designed with a Power-
Off disable allowing 聯(lián)live insertion聰 of boards when used as
backplane drivers.
The PI74FCT162244T has 鹵24mA balanced output drivers. It is
designed with current limiting resistors at its outputs to control the
output edge rate resulting in lower ground bounce and undershoot.
This eliminates the need for external terminating resistors for most
interface applications.
The PI74FCT162H244T has 聯(lián)Bus Hold聰 which retains the input聮s
last state whenever the input goes to high-impedance preventing
聯(lián)floating聰 inputs and eliminating the need for pull-up/down
resistors.
Logic Block Diagram
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PS2031D
05/17/99
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