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PI74AVC+16841A Datasheet

  • PI74AVC+16841A

  • 10-Bit D-Type Latch

  • 10頁

  • ETC

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PI74AVC+16841
2.5V 20-Bit Bus Interface D-Type
Latch with 3-State Outputs
Product Features
PI74AVC
+
16841 is designed for low-voltage operation,
V
CC
= 1.65V to 3.6V
True 鹵24mA Balanced Drive @ 3.3V
I
OFF
supports partial power-down operation
3.6V I/O Tolerant Inputs and Outputs
聲 All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
Industrial operation: 聳40擄C to +85擄C
Available Packages:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor聮s PI74AVC+ series of logic circuits are
produced using the Company聮s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16841, a 20-bit bus-interface D-type latch, is designed
for 1.65V to 3.6V V
CC
operation.
The device features 3-state outputs designed specifically for
driving highly capacitive or relatively low-impedance loads.
It is particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The device can be used as two 10-bit latches or one
20-bit latch (transparent D-type). The device has noninverting Data
(D) inputs and provides true data at its outputs. While the Latch
Enable (1LE or 2LE) input is HIGH, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken LOW, the Q
outputs are latched at the levels set up at the D inputs.
A buffered Output Enable (1OE or 2OE) input can be used to place
the outputs of the corresponding 10-bit latch in either a normal logic
state (high or low logic levels) or a high-impedance state. In that
state, outputs neither load nor drive the bus lines significantly.
Logic Block Diagram
1OE
1LE
1
56
C1
2
1Q1
1D1
55
1D
The Output Enable (OE) input does not affect the internal operation
of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
TO NINE OTHER CHANNELS
2OE
2LE
28
29
C1
15
2Q1
2D1
42
1D
TO NINE OTHER CHANNELS
1
PS8549
07/31/01

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