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PI74AVC+16836A Datasheet

  • PI74AVC+16836A

  • 20-Bit Buffer/Driver

  • 98.76KB

  • 9頁

  • ETC

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PI74AVC+16836
2.5V 20-Bit Universal Bus
Driver with 3-State Outputs
Product Features
鈥?/div>
PI74AVC
+
16836 is designed for low voltage operation,
V
CC
= 1.65V to 3.6V
鈥?/div>
True 鹵24mA Balanced Drive @ 3.3V
鈥?/div>
I
OFF
supports partial power-down operation
鈥?/div>
3.6V I/O Tolerant inputs and outputs
鈥?/div>
Meets PC133 SDRAM Registered DIMM Specifications
鈥?All outputs contain a patented DDC
(Dynamic Drive Control) circuit that reduces noise without
degrading propagation delay
鈥?Industrial operation at 鈥?0擄C to +85擄C
鈥?Available Packages:
鈥?56-pin 240 mil wide plastic TSSOP (A)
鈥?56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor鈥檚 PI74AVC+ series of logic circuits are
produced using the Company鈥檚 advanced 0.35 micron CMOS
technology, achieving industry leading speed.
The 20-bit PI74AVC+16836 universal bus driver is designed
for 1.65V to 3.6V Vcc operation.
Data flow from A to Y is controlled by the Output Enable (OE) input.
The device operates in the transparent mode when the latch-enable
(LE) input is LOW. When LE is HIGH, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is HIGH,
the A data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state, but all the inputs are enabled and data is capable
of being stored in the register.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
1
OE
56
CLK
LE
29
A1
55
1D
C1
CLK
2
Y1
1
PS8511A
02/06/01

PI74AVC+16836A 產品屬性

  • 35

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74AVC+

  • 通用總線驅動器

  • -

  • 20 位

  • 24mA，24mA

  • 1.65 V ~ 3.6 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

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