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PI74AVC+16652
2.5V 16-Bit Bus Transceiver and
Register with 3-State Outputs
Product Features
聲
PI74AVC
+
16652 is designed for low-voltage operation,
V
CC
= 1.65V to 3.6V
聲
True 鹵24mA Balanced Drive @ 3.3V
聲
I
OFF
supports partial power-down operation
聲
3.6V I/O Tolerant Inputs and Outputs
聲 All outputs contain a patented DDC
(Dynamic DriveControl) circuit that reduces noise without
degrading propagation delay.
聲 Industrial operation: 聳40擄C to +85擄C
聲 Available Packages:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor聮s PI74AVC+ series of logic circuits are
produced using the Company聮s advanced submicron CMOS
technology, achieving industry leading speed.
The PI74AVC+16652 is a 16-bit bus transceiver and register
designed for low 1.65V to 3.6V V
CC
operation. It consists of D-type
flip-flops and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal storage
registers. The device can be used as two 8-bit transceivers or one
16-bit transceiver.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A low input level selects real-time data, and a high
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock (CLKAB
or CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA. In this configuration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are in the
high-impedance state, each set of bus lines remains at its last level
configuration.
To ensure the high-impedance state during power up or power
down, OEBA should be tied to V
CC
through a pull-up resistor and
OEAB should be tied to GND through a pull-down resistor; the
minimum value of the resistor is determined by the current-sinking
current sourcing capability of the driver.
Logic Block Diagram
1OEBA
56
1OEAB
1
1CLKBA
1SBA
1CLKAB
1SAB
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
TO SEVEN OTHER CHANNELS
2OEBA
29
2OEAB
28
2CLKBA
2SBA
2CLKAB
2SAB
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
TO SEVEN OTHER CHANNELS
1
PS8550
07/31/01
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