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PI74ALVCHT16245V Datasheet

  • PI74ALVCHT16245V

  • Dual 8-bit Bus Transceiver

  • 249.45KB

  • 4頁

  • ETC

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PI74ALVCHT16245
3.3V 16-Bit Bidirectional Transceiver
with 3-State Output
Product Features
鈥?/div>
PI74ALVCHT16245 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
5V I/O Tolerant
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-state
eliminating the need for external pull-up resistors
鈥?/div>
Industrial operation at -40擄C to +85擄C
鈥?/div>
Packages available:
聳 48-pin 240-mil wide plastic TSSOP (A)
聳 48-pin 300-mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed grades.
The PI74ALVCHT16245 is a 16-bit bidirectional transceiver designed
for asynchronous two-way communication between data buses.
The direction control input pin (xDIR) determines the direction of
data flow through the bidirectional transceiver. The Direction and
Output Enable controls are designed to operate this device as either
two independent 8-bit transceivers or one 16-bit transceiver. The
output enable (OE) input, when HIGH, disables both A and B ports
by placing them in HIGH Z condition.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current sinking
ability of the driver.
The PI74ALVCHT16245 has 聯(lián)Bus Hold聰 which retains the data
input聮s last state whenever the data input goes to high-impedance
preventing 聯(lián)floating聰 inputs and eliminating the need for pullup/
down resistors.
The PI74ALVCHT16245 can be driven from either 3.3V or 5.0Vdevices
allowing this device to be used as a translator in a mixed 3.3/5.0V
system.
2
DIR
Logic Block Diagram
1
DIR
1
OE
2
OE
1
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
3
1
B
3
1
A
4
1
B
4
1
A
5
1
B
5
1
A
6
1
B
6
1
A
7
1
B
7
2
A
0
2
B
0
2
A
1
2
B
1
2
A
2
2
B
2
2
A
3
2
B
3
2
A
4
2
B
4
2
A
5
2
B
5
2
A
6
2
B
6
2
A
7
2
B
7
1
PS8308
07/30/98

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