鈥?/div>
PI74ALVCHR162524 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
A & B parts have equivalent 26 Ohm series resistors
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCHR162524 data flow in each direction is controlled by
output-enable (OEAB and OEBA) and clock-enable (CLKENBA)
inputs. For the A-to-B data flow, the data flows through a single
buffer. The B-to-A data can flow through a four-stage pipeline
register path, or through a single register path, depending on the
state of the select (SEL) input.
Data is stored in the internal registers on the low-to-high
transition of the clock (CLK) input, provided that the appropriate
CLKENBA input is low. The B-to-A data transfer is synchronized
with CLK.
To reduce overshoot and undershoot, the A and B-port outputs
include 26-ohm series resistors.
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pull-up resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
The PI74ALVCHR162524 has 聯(lián)Bus Hold聰 which retains the data
input聮s last state whenever the data input goes to high-impedance
preventing 聯(lián)floating聰 inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
CLK
CLKENBA
OEAB
OEBA
SEL
30
28
2
27
55
1 of 18 Channels
CE
A1
G1
1
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
3
C1
1D
54
B1
To 17 Other Channels
1
PS8314B
11/06/00
1
2
3
4
5
6
7
