音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PI74ALVCHR162245 Datasheet

  • PI74ALVCHR162245

  • 3.3V 16-Bit Bidirectional Transceiver with 3-State Output

  • 249.76KB

  • 4頁(yè)

  • PERICOM   PERICOM

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCHR162245
3.3V 16-Bit Bidirectional Transceiver
with 3-State Output
Product Features
聲 PI74ALVCHR162245 is designed for low voltage operation
聲 Vcc = 2.3V to 3.6V
聲 Hysteresis on all inputs
聲 Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
聲 Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
聲 All output ports have equivilent 26鈩?series resistors:
No external resistors are required
聲 Bus Hold retains last active bus state during 3-state
eliminating the need for external pull-up resistors
聲 Industrial operation at -40擄C to +85擄C
聲 Packages available:
聳 48-pin 240-mil wide plastic TSSOP (A)
聳 48-pin 300-mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology to achieve industry-leading speed grades.
The PI74ALVCHR162245 is a 16-bit bidirectional transceiver
designed for asynchronous two-way communication between data
buses. The direction control input pin (xDIR) determines the
direction of data flow through the bidirectional transceiver. The
Direction and Output Enable controls are designed to operate this
device as either two independent 8-bit transceivers or one 16-bit
transceiver. The output enable (OE) input, when HIGH, disables
both A and B ports by placing them in HIGH Z condition.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current sinking
ability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
DIR
2
DIR
1
OE
2
OE
1
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
3
1
B
3
1
A
4
1
B
4
1
A
5
1
B
5
1
A
6
1
B
6
1
A
7
1
B
7
2
A
0
2
B
0
2
A
1
2
B
1
2
A
2
2
B
2
2
A
3
2
B
3
2
A
4
2
B
4
2
A
5
2
B
5
2
A
6
2
B
6
2
A
7
2
B
7
1
PS8343
10/09/98

PI74ALVCHR162245相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門(mén)IC型號(hào)推薦

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買(mǎi)家服務(wù):
賣(mài)家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào),
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn),您的參與是維庫(kù)提升服務(wù)的動(dòng)力!意見(jiàn)一經(jīng)采納,將有感恩紅包奉上哦!