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PI74ALVCH32245NB Datasheet

  • PI74ALVCH32245NB

  • Quad 8-bit Bus Transceiver

  • 161.54KB

  • 7頁(yè)

  • ETC

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PI74ALVCH32245
3.3V, 32-Bit Bidirectional Transceiver
with 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH32245 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
> 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA (NB)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed grades.
The PI74ALVCH32245 is a 32-bit bidirectional transceiver
designed for asynchronous two-way communication between
data buses. The direction control input pin (xDIR) determines
the direction of data flow through the bidirectional transceiver.
The Direction and Output Enable controls are designed to operate
this device as either four independent 8-bit transceivers, two 16-Bit
transceivers, or one 32-Bit transceiver. The output enable (OE)
input, when HIGH, disables both A and B ports by placing them in
HIGH Z condition.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the
minimum value of the resistor is determined by the current sinking
ability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram (Positive Logic)
1DIR A3
A4 1OE
1A1
A5
A2
1B1
2A1 E5
E2
2B1
2DIR H3
H4 2OE
To Seven Other Channels
To Seven Other Channels
3DIR J3
J4 3OE
3A1 J5
J2
3B1
4DIR T3
T4 4OE
4A1 N5
N2
4B1
To Seven Other Channels
To Seven Other Channels
1
PS8437
08/24/01

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