鈥?/div>
PI74ALVCH16952 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-STATE
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 48-pin 240 mil wide plastic TSSOP (A)
聳 48-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16952 16-bit registered transceiver is designed for
2.3V to 3.6V V
CC
operation.
The product contains two sets of D-type flip-flops for temporary
storage of data flowing in either direction. The device can be used
as two 8-bit transceivers or one 16-bit tranceiver. Data on the A or
B bus is stored in the registers on the low-to-high transition of the
clock (CLKAB or CLKBA) input provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the output-enable
(OEAB or OEBA) input low accesses the data on either port.
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pull-up resistor; the minimum
value of the resistor is determined by the current-sinking capability
of the driver.
The PI74ALVCH16952 has 聯(lián)Bus Hold聰 which retains the data
input聮s last state whenever the data input goes to high-impedance
preventing 聯(lián)floating聰 inputs and eliminating the need for pullup/
down resistors.
3
2
56
54
55
1
1CLKENBA
1CLKBA
1OEAB
Logic Block Diagram
1CLKENAB
1CLKAB
1OEBA
One of Eight
Channels
1A1
5
C1
CE
1D
C1
CE
1D
C1
CE
1D
C1
CE
1D
V
52
1B1
42
2B1
PS8197A
10/16/00
V
1
PERICOM
1
2
3
4
5
