音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PI74ALVCH16835V Datasheet

  • PI74ALVCH16835V

  • 18-Bit Buffer/Driver

  • 5頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH16835
18-Bit Universal Bus Driver
with 3-STATE Outputs
Product Features
鈥?/div>
PI74ALVCH16835 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
聳 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74ALVCH16835 universal bus driver is designed for
2.3V to 3.6V Vcc operation.
Data flow from A to Y is controlled by Output Enable (OE). The
device operates in the transparent mode when LE is HIGH. The A
data is latched if CLK is held at a high or low logic level. If LE is
LOW, the A-bus is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
Logic Block Diagram
OE
27
CLK
30
28
LE
54
A1
1D
C1
CLK
3
Y1
TO 17 OTHER CHANNELS
1
PS8169A
07/30/98

PI74ALVCH16835V相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！