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Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed
for 2.3V to 3.6V V
CC
operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-
impedance loads. This device is particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus
drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one
18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the
D-type flip-flops enter data on the low-to-high transitions of the
clock. Taking CLKEN HIGH disables the clock buffer, thus
latching the outputs. Taking the Clear (CLR) input LOW causes the
Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
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PS8103 04/03/97
PERICOM
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