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PI74ALVCH16821V Datasheet

  • PI74ALVCH16821V

  • 20-Bit D-Type Flip-Flop

  • 296.38KB

  • 5頁(yè)

  • ETC

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PI74ALVCH16821
3.3V 20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH16821 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16821 is a 20-bit bus interface flip-flop designed
for 2.3V to 3.3V V
CC
operation. It can be used as two 10-bit flip-
flops or one 20-bit flip-flops. The 20 flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-
impedance state and increased drive provide the capacity to drive
bus lines without the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
OE
1
2
OE
28
1CLK 56
One of Ten
Channels
2CLK 29
One of Ten
Channels
1
Q
1
C
1
1
D
1D
1
55
2
C
1
1
D
2D
1
42
15
2Q
1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1
PS8156
11/17/97

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