鈥?/div>
PI74ALVCH16721 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH16721 is a 20-bit flip-flop with 3-state outputs
designed specifically for 2.3V to 3.6V V
CC
operation. The
PI74ALVCH16721 is designed with edge-triggered D-type flip-
flops with qualified clock storage. On the positive transition of
clock (CLK) input, the device provides true data at the Q outputs,
provided that the clock-enable (CLKEN) input is LOW. If CLKEN
is HIGH, no data is stored.
A buffered output-enable (OE) input can be used to place the
20 outputs in either a normal logic state (HIGH or LOW level) or
a high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capacity to drive bus lines
without the need for interface or pullup components. OE does not
affect the internal operation of the flip-flops. Old data can be
retained or new data can be entered while the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH16721 data has 聯(lián)Bus Hold聰 which retains the
data input聮s last state whenever the data input goes to high-
impedance preventing 聯(lián)floating聰 inputs and eliminating the need
for pullup/down resistors.
Logic Block Diagram
1
56
29
2
55
1
PS8090C 02/07/00
1
2
3
4
5
