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PI74ALVCH16652 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-State,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH16652 is a 16-bit bus transceiver and register
designed for low 2.3V to 3.6V Vcc operation. It consists of D-type
flip-flops and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal storage
registers. The device can be used as two 8-bit transceivers or one 16-
bit transceiver.
Complementary Output Enable (OEAB and OEBA) inputs are
provided to control the transceiver functions. Select Control (SAB
and SBA) inputs are provided to select whether real-time or stored
data is transferred. A low input level selects real-time data, and a high
input level selects stored data. Circuitry used for Select Control
eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data.
Data on the A or B bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock (CLKAB or
CLKBA) inputs regardless of the levels on the Select Control or
Output Enable inputs. When SAB and SBA are in the real-time
transfer mode, it also is possible to store data without using the
internal D-type flip-lops by simultaneously enabling OEAB and
OEBA. In this configuration, each output reinforces its input. Thus,
when all other data sources to the two sets of bus lines are in the high-
impedance state, each set of bus lines remains at its last level
configuration.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
To ensure the high-impedance state during power up or power down,
OEBA should be tied to Vcc through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistor; the minimum
value of the resistor is determined by the current-sinking current
sourcing capability of the driver.
Product Pin Configuration
1
OEAB
1
CLKAB
1
SAB
GND
1
A
1
1
A
2
V
CC
1
A
3
1
A
4
1
A
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
2
A
4
2
A
5
2
A
6
V
CC
2
A
7
2
A
8
GND
2
SAB
2
CLKAB
2
OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin
A,V
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
SBA
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
GND
2
B
4
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
GND
2
SBA
2
CLKBA
2
OEBA
1
PS8135B
11/06/00
1
2
3
4
5
6
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