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PI74ALVCH16374V Datasheet

  • PI74ALVCH16374V

  • 16-Bit D-Type Flip-Flop

  • 5頁(yè)

  • ETC

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PI74ALVCH16374
16-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Features
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PI74ALVCH16374 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-STATE
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 48-pin 240 mil wide plastic TSSOP (A)
聳 48-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 16-bit edge-triggered D-type flip-flop is designed for 2.3V to
3.6V V
CC
operation.
The PI74ALVCH16374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as two 8-bit flip-flops or one
16-bit flip-flop. On the positive transition of the Clock (CLK)
input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs. OE can be used to place the eight outputs in
either a normal logic state (high or low logic levels) or a high-
impedance state. In that state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased
drive provide the capability to drive bus lines without need for
interface or pullup components. OE does not affect internal
operations of the flip-flop. Old data can be retained or new data can
be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
C1
2
Logic Block Diagram
1OE
1
1CLK
48
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
1Q1
1D1
47
1D
To Seven Other Channels
24
2OE
2CLK
25
C1
13
2Q1
2D1
36
1D
To Seven Other Channels
1
PS8138A 09/03/98

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