鈥?/div>
PI74ALVCH162827 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Output ports have equivalent 26鈩?series resistors;
no external resistors are required
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced using the Company聮s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The PI74ALVCH162827 is a 20-bit non-inverting buffer/driver
designed for 2.3V to 3.6V V
CC
operation.
The buffer/driver is composed of two 10-bit sections with separate
output-enable signals. For either 10-bit buffer section, the two
output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
both be low for the corresponding Y outputs to be active. If either
output-enable input is HIGH, the outputs of that 10-bit buffer
section are in the high-impedance state.
The outputs, which are designed to sink up to 12mA, include 26鈩?/div>
resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH162827 has 聯(lián)Bus Hold聰 which retains the data
input聮s last state whenever the data input goes to high-impedance
preventing 聯(lián)floating聰 inputs and eliminating the need for pullup/
down resistors.
Logic Block Diagram
1
OE
1
1
OE
2
1
56
2
OE
1
2
OE
2
28
29
1
A
1
55
2
1
Y
1
2
A
1
42
15
2
Y
1
To 9 Other Channels
To 9 Other Channels
1
PS8095B 10/07/98
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2
3
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