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PI74ALVCH162820V Datasheet

  • PI74ALVCH162820V

  • 10-Bit D-Type Flip-Flop

  • 6頁

  • ETC

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PI74ALVCH162820
3.3V 10-Bit Flip-Flop with Dual Outputs
and 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH162820 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Output ports have equivalent 26鈩?series resistors,
no external resistors are required.
鈥?/div>
Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
鈥?/div>
Industrial operation at 聳40擄C to +85擄C
鈥?/div>
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH162820 is a 10-bit flip-flop designed for 2.3V to 3.3V
V
CC
operation. The PI74ALVCH162820 is designed with edge-
triggered D-type flip-flops. On the positive transition of clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components. OE does not affect the
internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance
state.
The outputs, which are designed to sink up to 12mA, include
26鈩?resistors to reduce overshoot and undershoot.
The PI74ALVCH162820 has 聯(lián)Bus Hold聰 which retains the data
input聮s last state whenever the data input goes to high-impedance
preventing 聯(lián)floating聰 inputs and eliminating the need for pullup/
down resistors.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
PS8094B
09/26/00

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