音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

PI74ALVCH162820 Datasheet

  • PI74ALVCH162820

  • 3.3V 10-Bit Flip-Flop with Dual Outputs and 3-State Outputs

  • 274.12KB

  • 5頁

  • PERICOM   PERICOM

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCH162820
3.3V 10-Bit Flip-Flop with Dual Outputs
and 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH162820 is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Output ports have equivalent 26鈩?series resistors,
no external resistors are required.
鈥?/div>
Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
鈥?/div>
Industrial operation at 鈥?0擄C to +85擄C
鈥?/div>
Packages available:
鈥?56-pin 240 mil wide plastic TSSOP (A)
鈥?56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor鈥檚 PI74ALVCH series of logic circuits are
produced in the Company鈥檚 advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH162820 is a 10-bit flip-flop designed for 2.3V to 3.3V
V
CC
operation. The PI74ALVCH162820 is designed with edge-
triggered D-type flip-flops. On the positive transition of clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components. OE does not affect the
internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance
state.
The outputs, which are designed to sink up to 12mA, include
26鈩?resistors to reduce overshoot and undershoot.
The PI74ALVCH162820 has 鈥淏us Hold鈥?which retains the data
input鈥檚 last state whenever the data input goes to high-impedance
preventing 鈥渇loating鈥?inputs and eliminating the need for pullup/
down resistors.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
PS8094A 03/26/97

PI74ALVCH162820相關(guān)型號(hào)PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！