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PI74ALVCH16270 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 聳40擄C to +85擄C
Packages available:
聳 56-pin 240 mil wide plastic TSSOP (A)
聳 56-pin 300 mil wide plastic SSOP (V)
Pericom Semiconductor聮s PI74ALVCH series of logic circuits are
produced in the Company聮s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI7ALVCH16270 is used in applications where data must
be transferred from a narrow high-speed bus to a wider lower
frequency bus.
The device provides synchronous data exchange between the two
ports. Data is stored in the internal registers on the
low-to-high transition of the clock (CLK) input when the appropriate
CLKEN inputs are low. The select (SEL) line selects 1B or 2B
data for the A outputs. For data transfer in the A-to-B direction, a
two stage pipeline is provided in the A-to1B path,with a single
storage register in the A-to-2B path. Proper control of the CLKENA
inputs allows two sequential 12-bit words to be presented
synchronously as a 24-bit on the B port. Data flow is controlled by
the active-low output enables (OEA, OEB). The control terminals
are registered to synchronize the bus direction changes with the
CLK.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor, the
minimum value of the resistor is determined by the current-sinking
capability of the driver. Due to OE being routed through a register,
the active state of the outputs cannot be determined prior to the
arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
PS8171A
03/17/98
1
2
3
4
5
