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PI74ALVCH1622601 Datasheet

  • PI74ALVCH1622601

  • 18-Bit Universal Bus Transceiver With 3-State Outputs

  • 5頁

  • PERICOM   PERICOM

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PI74ALVCH1622601
18-Bit Universal Bus Transceiver
With 3-State Outputs
Product Features
鈥?/div>
PI74ALVCH1622601is designed for low voltage operation
鈥?/div>
V
CC
= 2.3V to 3.6V
鈥?/div>
Hysteresis on all inputs
鈥?/div>
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25擄C
鈥?/div>
Inputs/Outputs have equivalent 26鈩?series resistors,
no external resistors are required.
鈥?/div>
Bus Hold retains last active bus state during 3-state
eliminates the need for external pullup resistors
鈥?/div>
Industrial operation at 鈥?0擄C to +85擄C
鈥?/div>
Packages available:
鈥?56-pin 240 mil wide plastic TSSOP (A)
鈥?56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor鈥檚 PI74ALVCH series of logic circuits are
produced in the Company鈥檚 advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCH1622601 uses D-type latches and D-type flip-
flops with 3-state outputs to allow data flow in transparent, latched,
and clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
and OEBA), Latched Enable (LEAB and LEBA), and Clock
(CLKAB and CLKBA) inputs. The clock can be controlled by the
Clock Enable (CLKENAB and CLKENBA) inputs. For A-to-B
data flow, the device operates in the transparent mode when LEAB
is HIGH. When LEAB is LOW, the A data is latched if CLKAB is
held at a high or low logic level. If LEAB is low, the A-bus is stored
in the latch/flip-flop on the low-to-high transition of CLKAB.
When OEAB is low, the outputs are active. When OEAB is HIGH,
the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, CLKBA, and CLKENBA.
To reduce overshoot and undershoot, the inputs/outputs include
26鈩?series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
The PI74ALVCH1622601 has 鈥淏us Hold鈥?which retains the data
input鈥檚 last state whenever the data input goes to high-impedance
preventing 鈥渇loating鈥?inputs and eliminating the need for pullup/
down resistors.
1
PS8115B
02/03/98

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