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PI6C9911E-2I Datasheet

  • PI6C9911E-2I

  • Eight Distributed-Output Clock Driver

  • 9頁

  • ETC

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TEST
31
GND
REF
3F0
FB
REF
Phase
Freq
Det
Filter
FS
Vco and
Time Unit
Generator
4Q0
4Q1
SKEW
SELECT
MATRIX
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
4
3
2
1
32
30
29
28
2F1
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
27
26
25
24
23
22
21
20
TEST
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
Three Level
Select Inputs
VCCN
VCCQ
FS
VCCN
3Q1
3Q0
2Q1
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1
2Q0
FB
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1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C9911 & PI6C9911E
5V High-Speed Programmable Skew
Clock Buffers -
SuperClock聶
Product Features
鈥?/div>
Four pairs of programmable skew outputs
鈥?/div>
User-selectable output functions:
鈭?/div>
Selectable skews
鈭?/div>
Inverted and noninverted
鈭?/div>
Operation at 錕?frac12; and 錄 input frequency
鈭?/div>
Operation at 2X and 4X input frequency
鈥?/div>
Low skew <100ps typical same pair, 250ps max.
鈥?/div>
Allow REF clock input to have Spread Spectrum
modulation for EMI reduction
鈥?/div>
2X, 4X, 錕?frac12; and 錄 outputs
鈥?/div>
3-level inputs for skew and output frequency control
鈥?/div>
External feedback, internal loop filter
鈥?/div>
Low cycle-to-cycle Jitter: <25ps RMS
鈥?/div>
Duty cycle of output clock signals: 45% min. 55% max.
鈥?/div>
Same pinout as Cypress CY7B9911
鈥?/div>
Available in 32-pin PLCC Package (J)
鈥?/div>
Output Operation
3.75 to 100 MHz for PI6C9911
3.75 to 125 MHz for PI6C9911E
Description
The PI6C9911 and PI6C9911E are low-skew, low jitter, 5V phase-
lock-loop (PLL) programmable skew clock drivers, for
high-performance computing and networking applications. These
parts offer user-selectable skew-control of 4 output pairs, provid-
ing the timing delays necessary to optimize high-performance
clock-distribution circuits.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.
The PI6C9911 and PI6C9911E allow the REF clock input to have
Spread Spectrum modulation for EMI reduction.
Both buffers are pin-compatable with Cypress聮s RoboClock
CY7B9911, but with improved AC/DC characteristics.
The PI6C9911 and PI6C9911E also have the same pinout as
Cypress聮s CY7B9911and with balanced output drive.
Logic Block Diagram
Pin Configuration
32-Pin
J
PS8451
01/27/00

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