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PI6C991-5J Datasheet

  • PI6C991-5J

  • Eight Distributed-Output Clock Driver

  • 9頁

  • ETC

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TEST
GND
REF
3F0
FB
REF
Phase
Freq
Det
Filter
Vco and
Time Unit
Generator
4
3
2
1
32
31
30
29
28
2F1
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
27
26
25
24
23
22
21
20
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
SKEW
SELECT
MATRIX
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FS
TEST
Three Level
Select Inputs
VCCN
VCCQ
VCCN
3Q1
3Q0
2Q1
2Q0
FB
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C991
5V High-Speed Programmable
Skew Clock Buffer -
SuperClock
TM
Product Features
鈥?/div>
Four pairs of programmable skew outputs
鈥?/div>
3.75 to 80 MHz output operation
鈥?/div>
User-selectable output functions:
鈭?/div>
Selectable skews
鈭?/div>
Inverted and noninverted
鈭?/div>
Operation at 錕?frac12; and 錄 input frequency
鈭?/div>
Operation at 2X and 4X input frequency
鈥?/div>
Low skew <100ps typical, same pair. 250ps max.
鈥?/div>
Allow REF clock input to have Spread Spectrum
modulation for EMI reduction
鈥?/div>
2X, 4X, 錕?frac12; and 錄 outputs
鈥?/div>
3-level inputs for skew and output frequency control
鈥?/div>
External feedback, internal loop filter
鈥?/div>
Low cycle-to-cycle Jitter: <25ps RMS
鈥?/div>
Duty cycle of output clock signals: 45% min. 55% max.
鈥?/div>
Compatible with Pentium based processor
鈥?/div>
Same pinout as Cypress CY7B991
鈥?/div>
Packaged in Plastic 32-pin PLCC Package
Description
The PI6C991 is a low-skew, low jitter, 5V phase-lock loop (PLL)
programmable skew clock driver, for high performance comput-
ing and networking applications. This part offers user selectable
skew-control of 4 output pairs, providing the timing delays neces-
sary to optimize high performance clock distribution circuits.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.
The PI6C991 allows the REF clock input to have Spread Spectrum
modulation for EMI reduction.
The PI6C991 is pin-compatible with Cypress RoboClock CY7B991,
with improved AC/DC characteristics.
Logic Block Diagram
Pin Configuration
32-Pin
J
1
PS8448
10/10/00

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