Features
聲 All output pair skew <100ps typical (250 Max.)
聲 12.5 MHz to 135 MHz output operation
聲 3.125 MHz to 135 MHz input operation
(input as low as 3.125 MHz for 4x operation, or
6.25 MHz for 2x operation)
聲 User-selectable output functions
聴 Selectable skew to 18ns
聴 Inverted and non-inverted
聴 Operation at 錕?frac12; and 錄 input frequency
聴 Operation at 2X and 4X input frequency
聲 Zero input-to-output delay
聲 50% duty-cycle outputs
聲 LVTTL outputs drive 50-ohm terminated lines
聲 Operates from a single 3.3V supply
聲 Low operating current
聲 32-pin PLCC package
聲 Jitter < 200ps peak-to-peak (< 25ps RMS)
聲 Available in LVTTL (PI6C39911) or Balanced (PI6C39912)
聲 PI6C39911 is a pin-to-pin compatible with CY7B9911V
Logic Block Diagram
Test
V
CCQ
REF
GND
2
1
FB
REF
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
1Q0
1Q1
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
3F0
FS
4
3
32 31
TEST
2F1
30
29
28
27
V
CCN
FB
V
CCN
3Q1
3Q0
1F0
1F1
1Q0
1Q1
1
2Q1
2Q0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer-SuperClock
廬
Description
The PI6C39911 and PI6C39912 offer selectable control over system
clock functions. These multiple-output clock drivers provide the
system integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50 ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to 鹵6 time
units from their nominal 聯(lián)zero聰 skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to 鹵12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Pin Configuration
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
4F0
4F1
Select Inputs
(three level)
4Q0
4Q1
Skew
Select
Matrix
3Q0
3Q1
2Q0
2Q1
32 Pin
J
26
25
24
23
22
21
3F0
3F1
2F0
2F1
14 15 16 17 18 19
20
PS8497C
04/10/01
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