PI6C2972
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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Low Voltage PLL Clock Driver
Features
鈥?Fully Integrated PLL
鈥?Output Frequency up to 125 MHz
鈥?Compatible with PowerPC and Pentium Microprocessors
鈥?3.3V V
CC
鈥?+ 100ps Typical Cycle鈥搕o鈥揅ycle Jitter
鈥?Packaging (Pb-free & Green available):
- 52-pin LQFP (FC)
Description
The PI6C2972 are 3.3V compatible, PLL based clock driver devices
targeted for high-performance CISC or RISC processor based sys-
tems. With output frequencies of up to 125 MHz and skews of 550ps
the PI6C2972 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync
output for added flexibility and ease of system implementation.
The PI6C2972 features an extensive level of frequency programma-
bility between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1,
2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges
of the Qa and Qc outputs. The Sync output will indicate when the
coincident rising edges of the above relationships will occur. The
Power鈥揙n Reset ensures proper programming if the frequency
select pins are set at power up. If the fselFB2 pin is held high, it may
be necessary to apply a reset after power鈥搖p to ensure synchroni-
zation between the QFB output and the other outputs. The internal
power鈥搊n reset is designed to provide this function, but with
power鈥搖p conditions being dependent, it is difficult to guarantee.
All other conditions of the fsel pins will automatically synchronize
during PLL lock acquisition.
The PI6C2972 offers a very flexible output enable/disable scheme.
Note that all of the control inputs on the PI6C2972 have internal pull鈥?/div>
up resistors.
The PI6C2972 is fully 3.3V compatible and requires no external loop
filter components. All inputs accept LVCMOS/LVTTL compatible
levels while the outputs provide LVCMOS levels with the capability
to drive 50-ohm transmission lines. For series terminated lines each
PI6C2972 output can drive two 50-ohm lines in parallel thus effec-
tively doubling the fanout of the device.
Pin Configuration
fselFB0
Ext_FB
GNDO
GNDO
VCCO
VCCO
GND0
VCCI
QFB
Qb0
Qb1
Qb2
Qb3
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GND0
VCO_Sel
39 38 37 36 35 34 33 32 31 30 29 28 27
26
40
41
42
43
44
45
46
47
48
49
50
51
52
1
2
3
4
5
6
7
8
25
24
23
22
21
20
19
18
17
16
15
14
9 10 11 12 13
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GND0
Inv_Clk
fselFB2
Frz_Data
PLL_EN
Ref_Sel
TClk_Sel
GND1
MR/OE
Frz_Clk
TClk0
TClk1
VCCA
xtal1
xtal2
1
PS8590C
09/22/04
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