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PI6C2516
Phase-Locked Loop Clock Driver
with 16 Clock Outputs
Product Features
聲 High Performance Phase-Locked Loop Clock Distribution for
Synchronous DRAM, server and networking applications.
聲 Zero Input-to-Output delay: Distribute One Clock Input
to four banks of four outputs, with separate output enables
for each bank.
聲 Allow Clock Input to have Spread Spectrum modulation for
EMI reduction. The clock outputs track the Clock Input
modulation.
聲 Maximum clock frequency of 150 MHz.
聲 Low jitter: Cycle-to-Cycle jitter 鹵100ps max
聲 Operates at 3.3V V
CC
聲 Available Packaging:
聳 48-pin TSSOP (Thin Shrink Small Outline) (A)
Description
The PI6C2516 family is a low-skew, low jitter, phase-locked loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM, server and networking applications. By connecting the
feedback FB_OUT output to the feedback FB_IN input, the propa-
gation delay from the CLK input to any clock output will be nearly
zero. This zero-delay feature allows the CLK input clock to be
distributed, providing 4 banks of four outputs.
For test purposes, the PLL can be bypassed by strapping the AV
CC
to ground.
The PI6C2516 family has the same pinout as the TI CDC2516, with
the added feature of allowing Spread Spectrum clock input.
Pin Description
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK
AGND
AGND
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
48-Pin
39
11
A
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FB_IN
AGND
FB_OUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
Block Diagram
1G
2G
3G
4G
4
4
4
1Y [0:3]
2Y [0:3]
3Y [0:3]
CLK
PLL
FB_IN
AVCC
4
4Y [0:3]
FB_OUT
1
PS8440C
07/24/01
PERICOM
1
2
3
4
5
6
7
