Product Features
聲 Operating Frequency up to 150 MHz
聲 Low-Noise Phase-Locked Loop Clock Distribution to meet
133 MHz Registered DIMM Synchronous DRAM module
specifications for server/workstation/PC applications
聲 Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
聲 Zero Input-to-output delay: Distribute One Clock Input to
one bank of five and one bank of four outputs, with
separate output enables
聲 Low jitter: Cycle-to-Cycle jitter 鹵75ps max.
聲 On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
聲 Operates at 3.3V V
CC
聲 Package: Plastic 24-pin TSSOP (L)
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PI6C2509-133
Low-Noise Phase-Locked Loop
Clock Driver with 9 Clock Outputs
Product Description
The PI6C2509-133 is a 聯(lián)quiet,聰 low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing low-noise clock signals for
SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing 5 clocks for the first bank, and an additional
4 clocks for the second bank.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV
CC
to ground.
Logic Block Diagram
1G
2G
CLK_IN
FB_IN
AV
CC
4
PLL
2Y[0:3]
5
Product Pin Configuration
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
1G
FB_OUT
24
1
23
2
22
3
4
24-Pin
21
20
5
L
19
6
18
7
17
8
16
9
15
10
14
11
13
12
CLK_IN
AV
CC
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
2G
FB_IN
1Y[0:4]
FB_OUT
1
PSXXXX
06/01/99
PERICOM
1
2
3
4
