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PI6C2502 Datasheet

  • PI6C2502

  • Phase-Locked Loop Clock Driver

  • 369.58KB

  • 6頁

  • PERICOM   PERICOM

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PI6C2502
2
Buffer
PI6C2502
Reference
Clock
Signal
V
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43212
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54321
210987651098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
43212
Phase-Locked Loop Clock Driver
Product Features
鈥?/div>
High-Performance Phase-Locked-Loop Clock Distribution
for Networking,
鈥?/div>
Synchronous DRAM modules for server/workstation/
PC applications
鈥?/div>
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
鈥?/div>
Zero Input-to-Output delay
鈥?/div>
Low jitter: Cycle-to-Cycle jitter 鹵100ps max.
鈥?/div>
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
鈥?/div>
Operates at 3.3V V
CC
鈥?/div>
Wide range of Clock Frequencies up to 80 MHz
鈥?/div>
Package: Plastic 8-pin SOIC Package (W)
Product Description
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
CLK_IN
FB_IN
AV
CC
PLL
CLK_OUT
FB_OUT
AGND
FB_OUT
1
2
3
4
CLK_OUT
V
CC
8-Pin
W
8
7
6
5
CLK_IN
AV
CC
GND
FB_IN
Feedback
Zero Delay
CLK_OUT
18 Output
Non-Zero
Delay
Buffer
17
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
1
PS8382B
03/20/02

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