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PI6C2405A-1 Datasheet

  • PI6C2405A-1

  • Clock IC | 5 Output Zero-Delay Clock Driver

  • 211.23KB

  • 7頁

  • ETC

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PI6C2405A
Zero-Delay Clock Buffer
Product Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 300ps
Internal feedback allows outputs to be synchronized
to the clock input
鈥?/div>
5V tolerant input*
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Operates at 3.3V V
DD
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Packages (Pb-free and Green available):
150-mil SOIC (W)
173-mil TSSOP (L)
* CLKIN must reference the same voltage thresholds for the
PLL to deliver zero delay skewing
Functional Description
The PI6C2405A is a PLL based, zero-delay buffer, with the ability
to distribute five outputs of up to 133MHz at 3.3V. All the outputs
are distributed from a single clock input CLKIN and output OUT0
performs zero delay by connecting a feedback to PLL.
An internal feedback on OUT0 is used to synchronize the outputs
to the input; the relationship between loading of this signal
and the outputs determines the input-output delay.
PI6C2405A is characterized for both commercial and industrial
operation.
PI6c2405A-1H is a high-drive version of PI6C2405A-1
Block Diagram: PI6C2405A
Pin Configuration: PI6C2405A
CLKIN
PLL
OUT0
OUT1
OUT2
OUT3
CLKIN
OUT2
OUT1
GND
1
2
3
4
8
OUT0
OUT4
V
DD
OUT3
8-Pin
W, L
7
6
5
PI6C2405A(鈥?, 鈥?H)
OUT4
Pin Description for PI6C2405A
Pin
1
2, 3, 5, 7
4
6
8
Signal
C LK IN
O UT[1- 4]
GN D
V
DD
O UT0
D e s cription
Input clock reference frequency (weak pull- down)
C lock outputs
Ground
3.3V supply
C lock output, internal PLL feedback (weak pull- down)
1
PS8592B
10/27/03

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