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PI6C2305-1HWI Datasheet

  • PI6C2305-1HWI

  • 3.3V Zero-Delay Buffer

  • 177.40KB

  • 6頁

  • PERICOM   PERICOM

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PI6C2305-1
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3.3V Zero-Delay Buffer
Features
鈥?/div>
Zero-input-output propagation delay
鈥?/div>
350ps phase error
鈥?/div>
Multiple low-skew outputs
鈥?Output-output skew less than 250ps
鈥?Device-device skew less than 700ps
鈥?/div>
10 MHz to 100 MHz operating range
鈥?/div>
Low Jitter <200ps
鈥?/div>
High drive option (PI6C2305-1H)
鈥?/div>
3.3V operation
鈥?/div>
Commercial Operation: 0擄C to +70擄C
鈥?/div>
Industrial Operation: 鈥?0擄C to +85擄C
鈥?/div>
Package: Space-saving 8-pin, 150-mil SOIC package (W)
Description
Providing five low-skew clocks, the PI6C2305-1 is a 3.3V zero-delay
buffer designed to distribute clock signals in applications including
PC, workstation, datacom, telecom, and high-performance systems.
The PI6C2305-1 provides 5 copies of clocks that have less than
350ps propagation delay compared to a reference clock. The skew
among the output clock signals for PI6C2305-1 is less than 250ps.
When there are no rising edges on the REF input, the PI6C2305-1
enters a power-down state. In this mode, the PLL is off and all outputs
are three-stated. This results in less than 50碌A(chǔ) of current draw.
Featuring faster rise and fall times, the PI6C2305-1H is the high-drive
version of the PI6C2305-1.
Block Diagram
Pin Configuration
REF
FBK
PLL
CLK0
CLK1
CLK2
CLK3
CLK4
REF
CLK2
CLK1
GND
1
2
3
4
8-Pin
W
8
7
6
5
CLK0
CLK4
V
DD
CLK3
Pin Description
Pin
1
2
3
4
5
6
7
8
Signal
REF
(1)
CLK2
(2)
CLK1
(2)
GND
CLK3
(2)
V
DD
CLK4
(2)
CLK0
(2)
De s cription
Input reference frequency, 5V Tolerant input
Buffered Clock output
Buffered Clock output
Ground
Buffered Clock output
3.3V Supply
Buffered Clock output
Buffered Clock output, internal feedback on this pin
Notes:
1. Weak pull-down.
2. Weak pull-down
on all outputs.
1
PS9477A
06/06/00

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