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Package:
Plastic 8-pin SOIC Package (W)
Product Description
The PI6C2302 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback CLK_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero. The PI6C2302
provides 2X CLK_IN on CLK_OUT output.
Application
If the system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The device-
to-device skew introduced can significantly reduce the perfor-
mance. Pericom recommends the use of a zero-delay buffer and an
eighteen output non-zero-delay buffer. As shown in
Figure 1, this combination produces a zero-delay buffer with all the
signal characteristics of the original zero-delay buffer, but with as
many outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Logic Block Diagram
Product Pin Configuration
CLK_IN
1
2
3
4
8-Pin
W
8
7
6
5
FB_IN
V
CC
GND
S
CLK_IN
FB_IN
S
梅2
PLL
CLK_OUT
AV
CC
AGND
CLK_OUT
Control Input
Feedback
S
1
18 Output
Output Source
PLL
CLK_IN
PLL Shutdown
N
Y
0
17
Zero Delay
CLK_OUT
Non-Zero
Delay
Buffer
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
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PS8418B
05/21/01
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