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PHB10N40 Datasheet

  • PHB10N40

  • PowerMOS transistor

  • 7頁

  • PHILIPS

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Philips Semiconductors
Product specification
PowerMOS transistor
PHB10N40
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
MAX.
400
10.7
147
0.55
UNIT
V
A
W
鈩?/div>
PINNING - SOT404
PIN
1
2
3
mb
gate
drain
source
drain
DESCRIPTION
PIN CONFIGURATION
mb
SYMBOL
d
g
2
1
3
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
I
D
I
DM
P
D
鈭哖
D
/鈭員
mb
V
GS
E
AS
I
AS
T
j
, T
stg
Continuous drain current
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Operating junction and
storage temperature range
CONDITIONS
T
mb
= 25 藲C; V
GS
= 10 V
T
mb
= 100 藲C; V
GS
= 10 V
T
mb
= 25 藲C
T
mb
= 25 藲C
T
mb
> 25 藲C
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
V
DD
鈮?/div>
50 V; starting T
j
= 25藲C; R
GS
= 50
鈩?
V
GS
= 10 V
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
10.7
6.7
43
147
1.176
鹵
30
520
10
150
UNIT
A
A
A
W
W/K
V
mJ
A
藲C
THERMAL RESISTANCES
SYMBOL
R
th j-mb
R
th j-a
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
TYP.
-
pcb mounted, minimum
footprint
50
MAX.
0.85
-
UNIT
K/W
K/W
April 1997
1
Rev 1.000

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