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PEEL22LV10AZTI-35 Datasheet

  • PEEL22LV10AZTI-35

  • ASIC

  • 139.54KB

  • 10頁(yè)

  • ETC

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Commercial/Industrial
PEEL鈩?22LV10AZ-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
鈥?/div>
Low Voltage, Ultra Low Power Operation
- Vcc = 2.7 to 3.6 V
- Icc = 5 碌A(chǔ) (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-B)
- 5 Volt tolerant inputs and I/O鈥檚
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 22V10
- Ideal for battery powered systems
- Replaces expensive oscillators
鈥?/div>
鈥?/div>
Architectural Flexibility
- Enhanced architecture fits in more logic
- 133 product terms x 44 input AND array
- 12 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
- Schmitt triggers on clock and data inputs
Schmitt Trigger Inputs
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
鈥?/div>
鈥?/div>
General Description
The PEEL22LV10AZ is a Programmable Electrically
Erasable Logic (PEEL) SPLD (Simple Programmable
Logic Device) that operates over the supply voltage
range of 2.7V-3.6V and features ultra-low, automatic
"zero" power-down operation. The PEEL22LV10AZ is
logically and functionally similar to ICT's 5V
PEEL22CV10A and PEEL22CV10AZ. The "zero power"
(25
碌A(chǔ)
max. I
CC
) power-down mode makes the
PEEL22LV10AZ ideal for a broad range of battery-
powered portable equipment applications, from hand-
held
meters
to
PCMCIA
modems.
EE-
reprogrammability provides both the convenience of
product fast reprogramming for product development
and quick personalization in manufacturing, including
Engineering Change Orders.
Figure 1 - Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
I
I
G ND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/CLK
I
I
I
I
I
I
I
I
I
I
G ND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
The differences between the PEEL22LV10AZ and
PEEL22CV10A include the addition of programmable
clock polarity, p-term clock, and Schmitt trigger input
buffers on all inputs, including the clock. Schmitt trigger
inputs allow direct input of slow signals such as
biomedical and sine waves or clocks. Like the
PEEL22CV10A, the PEEL22LV10AZ is a pin and
JEDEC compatible, logical superset of the industry
standard
PAL22V10
SPLD
Figure
1.
The
PEEL22LV10AZ provides additional architectural
features that allow more logic to be incorporated into
the design. The PEEL22LV10AZ architecture allows it
to replace over twenty standard 24-pin DIP, SOIC,
TSSOP
and
PLCC
packages.
Figure 2 - Block Diagram
CLK MUX (O ptiona l)
I
I
I
NC
I
I
I
4 3 2 1 28 27 26
5
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
I
I
I/CLK
NC
VCC
I/O
I/O
DIP
TSSOP
I/CLK
I
I
I
I
I
I
I
I
I
I
I
SP
AC
PEEL
T M
"AND"
ARRAY
OE
MACRO
CEL L
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
133 Terms
X
44 Inp uts
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
G ND
NC
I
I/O
I/O
I/CLK
I
I
I
I
I
I
I
I
I
I
G ND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
SP = SYNCHRONO US PRESET
AC = ASYNCHRONO US CLEAR
O E = O UTPUT ENABLE
PLCC
SOIC
1
04-02-037D

PEEL22LV10AZTI-35 產(chǎn)品屬性

  • Diodes Inc.

  • SPLD - 簡(jiǎn)單可編程邏輯器件

  • PEEL

  • 10

  • 27.7 MHz

  • 10

  • 35 ns

  • 3.3 V

  • 3 mA

  • + 85 C

  • - 40 C

  • TSSOP-24

  • SMD/SMT

  • 3.6 V

  • 2.7 V

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