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PEEL鈩?22CV10AZ -25

CMOS Programmable Electrically Erasable Logic Device

Features

Ultra Low Power Operation

- V

CC

= 5 Volts 鹵10%

- Icc = 10 碌A(chǔ) (typical) at standby

- Icc = 2 mA (typical) at 1 MHz

- t

PD

= 25ns.

CMOS Electrically Erasable Technology

- Superior factory testing

-

Reprogrammable in plastic package

-

Reduces retrofit and development costs

Development/Programmer Support

- Third party software and programmers

- Anachip PLACE Development Software

Architectural Flexibility

-

133 product terms x 44 input AND array

-

Up to 22 inputs and 10 I/O pins

-

12 possible macrocell configurations

-

Synchronous preset, asynchronous clear

-

Independent output enables

-

Programmable clock source and polarity

-

24-pin DIP/SOIC/TSSOP and 28-pin PLCC

Application Versatility

-

Replaces random logic

-

Pin and JEDEC compatible with 22V10

-

Ideal for power-sensitive systems

General Description

The PEEL鈩?2CV10AZ is a Programmable Electrically Erasable

Logic (PEEL鈩? device that provides a low power alternative to

ordinary PLDs. The PEEL鈩?2CV10AZ is available in 24-pin

DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A

鈥渮ero-power鈥?(100碌A(chǔ) max. I

CC

) standby mode makes the

PEEL鈩?2CV10AZ ideal for power sensitive applications such as

handheld meters, portable communication equipment and lap- top

computers/ peripherals. EE-reprogrammability provides the

convenience of instant reprogramming for development and a

reusable production inventory minimizing the impact of pro-

gramming changes or errors. EE-reprogrammability also

improves factory testability, thus ensuring the highest quality

possible.

The PEEL鈩?2CV10AZ is JEDEC file compatible with standard

22V10 PLDs. Eight additional configurations per macrocell (a

total of 12) are also available by using the 鈥?鈥?software/program-

ming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional

macrocell configurations allow more logic to be put into every

device, potentially reducing the design's component count and

lowering the power requirements even further.

Development

and

programming

support

for

the

PEEL鈩?2CV10AZ is provided by popular third-party program-

mers and development software. Anachip also offers free Win-

PLACE development software.

Figure 19 Block Diagram

Figure 19 Pin Configuration

I/CLK

I

I

I

I

I

I

I

I

I

I

GND

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

DIP

TSSOP

PLCC

SOIC

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent

accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

1/10

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