PEEL鈩?18CV8Z -25
CMOS Programmable Electrically Erasable Logic Device
Features
Ultra Low Power Operation
- Vcc = 5 Volts 鹵10%
- Icc = 10 碌A (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
CMOS Electrically Erasable Technology
- Superior factory testing
-
Reprogrammable in plastic package
-
Reduces retrofit and development costs
Application Versatility
-
Replaces random logic
-
Super set of standard PLDs
-
Pin and JEDEC compatible with 16V8
-
Ideal for use in power-sensitive systems
Architectural Flexibility
-
Enhanced architecture fits in more logic
-
113 product terms x 36 input AND array
-
10 inputs and 8 I/O pins
-
12 possible macrocell configurations
-
Asynchronous clear, Synchronous preset
-
Independent output enables
-
Programmable clock; pin 1 or p-term
-
Programmable clock polarity
-
20 Pin DIP/SOIC/TSSOP and PLCC
General Description
The PEEL鈩?8CV8Z is a Programmable Electrically Erasable
Logic (PEEL鈩? SPLD (Simple Programmable Logic Device)
that features ultra-low, automatic 鈥渮ero鈥?power-down operation.
The 鈥渮ero power鈥?(100 碌A max. Icc) power-down mode makes the
PEEL鈩?8CV8Z ideal for a broad range of battery-powered
portable equipment applications, from hand-held meters to PCM-
CIA modems. EE-reprogrammability provides both the conve-
nience of fast reprogramming for product development and quick
product personalization in manufacturing, including Engineering
Change Orders.
The PEEL鈩?8CV8Z is logically and functionally similar to
Anachip鈥檚 5 Volt PEEL鈩?8CV8 and 3 Volt PEEL鈩?8LV8Z.
The
differences
between
the
PEEL鈩?8CV8Z
and
PEEL鈩?8CV8 include the addition of programmable clock
polarity, a product term clock, and variable width product terms in
the AND/OR Logic Array.
Like the PEEL鈩?8CV8, the PEEL鈩?8CV8Z is logical superset
of the industry standard PAL16V8 SPLD. The PEEL鈩?8CV8Z
provides additional architectural features that allow more logic to
be incorporated into the design. Anachip鈥檚 JEDEC file translator
allows easy conversion of existing 20 pin PLD designs to the
PEEL鈩?8CV8Z architecture without the need for redesign. The
PEEL鈩?8CV8Z architecture allows it to replace over twenty
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.
Figure 7 Pin Configuration
I/CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Figure 8 Block Diagram
CLK MUX (Optional)
DIP
TSSOP
鈩?/div>
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
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