鈥?/div>
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 100K-ECL interfaced & buffered
Available in 16-pin DIP (600 mil) socket or SMD
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
data
3
廬
delay
devices,
inc.
PACKAGES
IN
A2
A1
VEE
A0
N/C
N/C
N/C
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
A2
A1
VEE
A0
N/C
N/C
N/C
PDU53-xx DIP
PDU53-xxM Military DIP
PDU53-xxC3 SMD
PDU53-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU53-series device is a 3-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends
on the address code (A2-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
PIN DESCRIPTIONS
IN
OUT
A2
A1
A0
VEE
GND
Signal Input
Signal Output
Address Bit 2
Address Bit 1
Address Bit 0
-5 Volts
Ground
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The
address is not latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Total programmed delay tolerance:
5% or 40ps,
whichever is greater
Inherent delay (TD
0
):
2.2ns typical
Address to input setup (T
AIS
):
2.9ns
Operating temperature:
0擄 to 85擄 C
Temperature coefficient:
100PPM/擄C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
鹵
0.7V
Power Supply Current:
-150ma typical (50鈩?to -2V)
Minimum pulse width:
3ns or 15% of total delay,
whichever is greater
Minimum period:
8ns or 2 x pulse width, whichever
is greater
A
i-1
PW
IN
IN
TD
A
OUT
Figure 1: Timing Diagram
漏
1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part
Number
PDU53-100
PDU53-200
PDU53-250
PDU53-400
PDU53-500
PDU53-750
PDU53-1000
PDU53-1200
PDU53-1500
PDU53-2000
PDU53-2500
PDU53-3000
Incremental Delay
Per Step (ps)
100
鹵
50
200
鹵
60
250
鹵
60
400
鹵
80
500
鹵
100
750
鹵
100
1000
鹵
200
1200
鹵
200
1500
鹵
200
2000
鹵
400
2500
鹵
400
3000
鹵
500
Total Delay
Change (ns)
0.70
1.40
1.75
2.80
3.50
5.25
7.00
8.40
10.50
14.00
17.50
21.00
A2-A0
A
i
T
OAX
T
AIS
NOTE: Any dash number between 100 and 3000
not shown is also available.
PW
OUT
Doc #98003
3/18/98
Powered by ICminer.com Electronic-Library Service CopyRight 2003
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU53-1200M相關(guān)型號(hào)PDF文件下載
-
型號(hào)
版本
描述
廠商
下載
-
英文版
Programmable 3-bit 100K ECL delay line
ETC
-
英文版
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 4-bit 100K ECL delay line
ETC
-
英文版
4-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Diode Standard 400V 5A Surface Mount PowerDI? 5
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
-
英文版
Delay Line
ETC
-
英文版
Programmable Delay Line
ETC
1
2
3
4
