鈥?/div>
Digitally programmable in 8 delay steps
Monotonic delay-versus-address variation
Precise and stable delays
Input & outputs fully 10KH-ECL interfaced & buffered
Fits standard 16-pin DIP socket
GND
ENB
1
2
16
15
data
3
廬
delay
devices,
inc.
PACKAGES
GND
OUT
IN
A0
VEE
6
7
8
10
9
A1
A2
GND
ENB
N/C
N/C
N/C
IN
A0
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
OUT
N/C
N/C
N/C
N/C
A1
A2
PDU108H-xx DIP
PDU108H-xxM Military DIP
PDU108H-xxC3 SMD
PDU108H-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU108H-series device is a 3-bit digitally programmable delay line.
The delay, TD
A
, from the input pin (IN) to the output pin (OUT) depends on
the address code (A2-A0) according to the following formula:
TD
A
= TD
0
+ T
INC
* A
PIN DESCRIPTIONS
IN
OUT
A2
A1
A0
ENB
VEE
GND
Signal Input
Signal Output
Address Bit 2
Address Bit 1
Address Bit 0
Output Enable
-5 Volts
Ground
where A is the address code, T
INC
is the incremental delay of the device,
and TD
0
is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 0.5ns
through 50ns, inclusively. The enable pin (ENB) is held LOW during
normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not
latched and must remain asserted during normal operation.
SERIES SPECIFICATIONS
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Total programmed delay tolerance:
5% or 1ns,
whichever is greater
Inherent delay (TD
0
):
2.8ns typical
Setup time and propagation delay:
Address to input setup (T
AIS
):
3.6ns
Disable to output delay (T
DISO
):
1.7ns typical
Operating temperature:
0擄 to 70擄 C
Temperature coefficient:
100PPM/擄C (excludes TD
0
)
Supply voltage V
EE
:
-5VDC
鹵
5%
Power Dissipation:
290mw typical (no load)
Minimum pulse width:
25% of total delay
DASH NUMBER SPECIFICATIONS
Part
Number
PDU108H-.5
PDU108H-1
PDU108H-2
PDU108H-3
PDU108H-5
PDU108H-10
PDU108H-20
PDU108H-40
PDU108H-50
Incremental Delay
Per Step (ns)
0.5
鹵
0.3
1.0
鹵
0.4
2.0
鹵
0.4
3.0
鹵
0.5
5.0
鹵
0.6
10.0
鹵
1.0
20.0
鹵
1.5
40.0
鹵
2.0
50.0
鹵
2.5
Total
Delay (ns)
3.5
鹵
1.0
7.0
鹵
1.0
14
鹵
1.0
21
鹵
1.0
35
鹵
1.7
70
鹵
3.5
140
鹵
7.0
280
鹵
14.0
350
鹵
17.5
NOTE: Any dash number between .5 and 50
not shown is also available.
漏
2001 Data Delay Devices
Doc #97043
10/1/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
PDU108H-20C3相關型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
3-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 3-bit TTL delay line
ETC
-
英文版
3-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
4-BIT PROGRAMMABLE DELAY LINE
ETC
-
英文版
4-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
4-BIT PROGRAMMABLE DELAY LINE
-
英文版
Programmable 5-bit TTL delay line
ETC
-
英文版
5-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 6-bit TTL delay line
ETC
-
英文版
6-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 7-bit TTL delay line
ETC
-
英文版
7-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 8-bit TTL delay line
ETC
-
英文版
8-BIT PROGRAMMABLE
DELAY LINE
DATA DELAY DEVI...
-
英文版
Programmable 3-bit 10K ECL delay line
ETC
-
英文版
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
DATA DELAY DEVI...
-
英文版
Power Outlet Strip; No. of Outlets:13; Outlet Type:NEMA 5-15...
-
英文版
POWER STRIP 20A 13 OUT RACK MNT
-
英文版
Power Outlet Strip; Supply Voltage:120VAC; No. of Outlets:13...
-
英文版
Suppressor; Suppressor Type:Outlet Strip; No. of Outlets:14;...
1
2
3
4
5
