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PCI2031 Datasheet

  • PCI2031

  • PCI-TO-PCI BRIDGE

  • 917.23KB

  • 70頁

  • TI

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PCI2031
PCI-TO-PCI BRIDGE
SCPS017A 鈥?DECEMBER 1997 鈥?REVISED JANUARY 1998
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PCI Power Management Compliant
ACPI 1.0 Compliant
Supports PCI Local Bus Specification 2.1
and PCI-to-PCI Bridge Specification 1.0
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
Supports Two 32-Bit, 33-MHz PCI Buses
Provides Internal Arbitration for Up to Six
Secondary Bus Masters With
Programmable Control
Provides Six Secondary PCI Bus Clock
Outputs
Supports Burst Transfers to Maximize Data
Throughput on Both PCI Buses
Provides Two Extension Windows
EEPROM Interface for Loading Texas
Instruments (TI鈩? Subsystem ID and
Subsystem Vendor ID
Four Primary and Four Secondary
General-Purpose I/Os
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Secondary Positive Decode
Independent Read and Write Buffers for
Each Direction
Predictable Latency: Compliant With PCI
Local Bus Specification 2.1
External Arbiter Option
Provides Concurrent Operation
Serial IRQ Bridging
Propagates Bus Locking
Supports PCI Clock Run
Secondary Bus Driven Low During Reset
Docking Connect Detects
PCI Local Bus Specification 2.0-Compliant
Device Optimization
Advanced Submicron, Low-Power CMOS
Technology
Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options
Packaged in 176-Pin Plastic Quad Flatpack
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Name/Terminal Number Sort Table . . . . . . . . . . . . . . . . . . 4
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction to the PCI2031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PCI Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bridge Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions for PCI Interface . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . .
PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . .
PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1998, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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